The present invention relates to a voltage booster circuit, and more particularly to a voltage booster circuit whereof output voltage is able to be controlled stably.
In known voltage booster circuits, there is a type wherein output voltage is controlled not to exceed a maximum value referring to a reference voltage. As an example of this type of voltage booster circuit, there is a prior art disclosed in a Japanese patent application laid open as a Provisional Publication No. 132088/'92, which is embodied for eliminating break of a clamping transistor provided for limiting maximum voltage of its output used for erasing or writing a non-volatile semiconductor memory.
FIG. 8 is a block diagram illustrating circuit configuration of the prior art having a plurality of pumping units 11-1 to 11-n. Each of them, a pumping unit 11-1 for example, comprises a serial connection of a first and a second nMOS transistors MN1 and MN2 each diode-connected, and a first and a second pumping capacitors C1 and C2.
A pumping clock generator 360 generates a pair of complementary pumping clocks Tc and Bc, one of which, the pumping clock Tc for instance, is supplied to gate/drain connection of the first nMOS transistor MN1 through the first pumping capacitor C1, while the other, the pumping clock Bc, is supplied to gate/drain connection of the second nMOS transistor MN2 through the second pumping capacitor C2, of each of the plurality of pumping units 11-1 to 11-n.
Drain of the first nMOS transistor MN1 is supplied with a positive supply Vcc through a diode connection of an input nMOS transistor NTr11. Drains of the first nMOS transistor of each of the following pumping units 11-2 to 11-n is supplied from source of the second nMOS transistor MN2 of each of their preceding pumping units 11-1 to 11-(n-1) and source of the last pumping unit 11-n connected to an output terminal VPUMP.
The output terminal VPUMP, which is connected to source of a pull-up nMOS transistor NTr12 diode connected with its gate and drain supplied from the positive supply Vcc, is also connected to an input of a voltage divider 320. Output level signal VPUMPC output from the voltage divider 320 is compared with a reference voltage VREF supplied from a reference voltage generator 340 by a differential amplifier 330 for obtaining a control signal, with which the pumping clock generator 360 is ON/OFF controlled.
When the output level signal VPUMPC, proportional to potential of the output terminal VPUMP, is lower than the reference voltage VREF, the differential amplifier 330 activates the pumping clock generator 360 with the control signal for generating the pair of complementary pumping clocks Tc and Bc, which drive the pumping capacitor C1 and C2 of every of the plurality of the pumping units 11-1 to 11-n to a HIGH and a LOW level, alternately and complementarily.
When the first pumping capacitor C1 of the first pumping unit 11-1 is pulled down by LOW level of the complementary pumping clock Tc, it is charged with the positive supply Vcc toward a voltage level (Vcc-Vth) through the input nMOS transistor NTr11, Vth being threshold voltage of the nMOS transistors, since the first nMOS transistor MN1 is made OFF with its source pushed up by the HIGH level of the other complementary pumping clock Bc. When the complementary pumping clock Tc is turned to HIGH level, the first pumping capacitor C1 is pushed up and its electric charge flows to the second pumping capacitor C2 through the second nMOS transistor MN2 becoming ON, the input nMOS transistor NTr11 becoming OFF in turn.
In the same way, electric charge is pumped up from drain of the first nMOS transistor MN1 to source of the second l nMOS transistor MN2 in each of the plurality of pumping units 11-1 to 11-n. Therefore, by repeating these pumping cycles, potential of the output terminal VPUMP is boosted up toward a potential (Vcc-Vth+.DELTA.V), .DELTA.V being a potential proportional to the number n of the pumping units 11-1 to 11-n and to peak-to-peak voltage of the complementary pumping clocks Tc and Bc and depending also on pulse widths of the pair of complementary pumping clocks Tc and Bc, for a certain range of output load of the voltage booster circuit.
The potential of the output terminal VPUMP is divided into the output level signal VPUMPC by the voltage divider 320, which is compared by the differential amplifier 330 with the reference voltage VREF generated from the reference voltage generator 340. So, the potential of the output terminal VPUMP is boosted up during VREF.gtoreq.VPUMPC until the pumping clock generator 360 is disabled when the output level signal VPUMPC becomes higher than the reference voltage VREF. Thus, an output voltage proportional to the reference voltage VREF is obtained from the output terminal VPUMP, in the prior art of FIG. 8.
There is also proposed another type of voltage booster circuits, wherein output potential is controlled by varying pulse widths of the complementary pumping clocks.
However, in the prior art of FIG. 8, there is a problem that it is difficult to maintain potential of the output terminal VPUMP accurately at a desired voltage proportional to the reference voltage VREF without somewhat overshooting or undershooting, because the voltage booster circuit, which should have a sufficient boosting ability compared to its generally varying load, can not be but ON/OFF controlled in the prior art.
On the other hand, in the another type of voltage booster circuits, there is another problem that a certainly complicated circuit configuration is needed for feedback-controlling pulse widths continuously according to output level of the voltage booster circuit, resulting in an increased power consumption.